1. Field of the Invention
The present invention relates to a memory.
2. Description of the Background Art
A ferroelectric memory comprising memory cells including ferroelectric capacitors is generally known as one of nonvolatile memories. Such ferroelectric memories include a one-transistor one-capacitor ferroelectric memory comprising memory cells each formed by one transistor and one ferroelectric capacitor, a one-transistor ferroelectric memory comprising memory cells each formed by one transistor having a ferroelectric capacitor and a crosspoint ferroelectric memory comprising memory cells each formed by only a ferroelectric capacitor arranged between a word line and a bit line. Each of the one-transistor ferroelectric memory and the crosspoint ferroelectric memory is constituted of a smaller number of elements as compared with the one-transistor one-capacitor ferroelectric memory, whereby the area per memory cell is reduced. Therefore, the chip area of the overall memory cell array can be reduced.
The one-transistor one-capacitor ferroelectric memory controls connection between bit lines and the ferroelectric capacitors through the transistors. Therefore, the parasitic capacitance of each bit line is the sum of the wiring capacitance thereof and the diffusion capacitance (junction capacitance) of the corresponding transistor. In the crosspoint ferroelectric memory, on the other hand, each ferroelectric capacitor is directly connected to the corresponding bit line, whereby the parasitic capacitance of the bit line is the sum of the wiring capacitance thereof and the capacitance of the ferroelectric capacitor. The dielectric constant of the ferroelectric capacitor is so high that the capacitance of the ferroelectric capacitor is greater than the diffusion capacitance (junction capacitance) of a transistor with respect to the same area. Therefore, the bit line parasitic capacitance in the crosspoint ferroelectric memory is greater than that in the one-transistor one-capacitor ferroelectric memory. Further, a read voltage output to the bit line in a read operation depends on the ratio (Cs/Cb) between a cell capacitance Cs and a bit line parasitic capacitance Cb. Therefore, the read voltage can be increased as the ratio Cs/Cb is increased. In other words, the read voltage can be more increased as the bit line parasitic capacitance Cb is reduced. However, the bit line parasitic capacitance in the crosspoint ferroelectric memory is greater than that in the one-transistor one-capacitor ferroelectric memory as hereinabove described, whereby the read voltage is disadvantageously reduced in the crosspoint ferroelectric memory.
A bit line hierarchical structure of bit lines divided into a main bit line and sub bit lines is also known in general. In this bit line hierarchical structure, a capacitance contributing to the bit line parasitic capacitance is limited to that of a ferroelectric capacitor forming a memory cell connected to the corresponding one of the divided sub bit lines. Thus, the value of the parasitic capacitance Cb of the overall bit lines is so reduced that the read voltage can be increased. In the bit line hierarchical structure, however, each nonselected sub bit line enters an electrically floating state, whereby noise is disadvantageously propagated to the sub bit line. Thus, the quantity of polarization of a ferroelectric capacitor linked to the nonselected sub bit line is deteriorated due to the voltage of the noise propagated to the sub bit line, to disadvantageously result in disappearance of data referred to as disturbance.
Therefore, generally proposed is a method of avoiding such disturbance caused in a ferroelectric capacitor linked to each nonselected sub bit line in a ferroelectric memory having the bit line hierarchical structure. According to this method, a common potential supply line (potential fixing line) is provided every two low blocks (subarrays) each including a sub bit line, while a transistor for connecting the corresponding sub bit line to the potential supply line is provided every sub bit line. The sub bit line connected to each nonselected low block (subarray) is connected to a fixed potential by turning on the transistor for connecting the sub bit line to the potential supply line (potential fixing line). Thus, the nonselected sub bit line can be prevented from entering a floating state.
According to this method, however, a potential supply line (potential fixing line) must be provided every two low blocks (subarrays), whereby the number of the potential supply lines (potential fixing lines) is disadvantageously increased if the number of the low blocks (subarrays) is increased. Therefore, the chip area of the ferroelectric memory is disadvantageously increased.